Due to the high market demand for new wireless technologies, there is great interest in developing differential structures such as, for example, frequency dividers that are able to efficiently operate at high frequencies with large division gain.
The frequency divider is one of the key building blocks of phase-locked loops (PLLs) in communications systems that use frequency synthesizers for wireless and Serial/Deserialized (Ser/Des) for wired/optical applications.
Current technology utilizes conventional twist-coupled toggle latch based frequency dividers that store electrical energy non-coherently in the parasitic capacitances. However, the conventional twist-coupled toggle latch based frequency dividers waste energy and generate noise through the charging/discharging process. A more power efficient topology that introduces less noise to the signal would be highly desirable for future wireless technologies such as RF/millimeter wave systems.
Typical divider designs are reported in the following literature and graphed in FIG. 7.    [1] M. Wurser, et al, “42 GHz Static Frequency Divider in a Si/SiGe Bipolar Technology,” ISSCC Digest of Tech. Papers, 1997, pp. 86-87.    [2] Z. Lao, et al., “55 GHz Dynamic Frequency Divider IC,” Elec. Let. 34 (20), 1998, pp. 1973-1974.    [3] A. Felder, et al., “Static Silicon Frequency Divider for Low Power Consumption (4 mW, 10 GHz) and High-Speed (160 mW, 19 GHz),” Proceedings, IEEE BCTM, 1992, pp. 159-162.    [4] B. Razavi, et al., “A 13.4 GHz CMOS Frequency Divider,” ISSCC Digest of Tech. Papers, 1994, pp. 176-177.    [5] H. Wang, “A 1.8V 3 mW 16.8 GHz Frequency Divider in 0.25 μm CMOS,” ISSCC Digest of Tech Papers, 2000, pp. 196-197.    [6] H, Knapp, et al., “25 GHz Static Frequency Divider and 25 GB/s Multiplexer in 0.12 μm CMOS,” ISSCC, Digest of Tech. Papers, 2002, pp. 302-303.    [7] Z. Lao, et al., “1.3V Supply Voltage 38 GHz Static Frequency Divider,” Elec. Let. 40 (5), 2004, pp. 295-296.    [8] M. Tiebout, “A CMOS Direct Injection-Locked Oscillator Topology as High-Frequency Low-Power Frequency Divider,” IEEE J. of Solid-State Circuits, 39 (7), 2004, pp. 1170-1174.    [9] J. Lee, at al., “A 40-GHz Frequency Divider in 0.18 μm CMOS Technology,” IEEE J. of Solid State Circuits 39 (4), 2004, pp. 594-601.
To overcome the deficiencies of the conventional twist-coupled toggle latch based frequency dividers, the present disclosure presents a new design that employs a phase-coherent transformer to obtain power-efficient, low phase noise frequency dividers that are tolerant of differential input phase mismatch.